Data networks use an assortment of switches, routers and traffic links to distribute the transmission of data. Oftentimes, the switches and routers employ interconnection networks consisting of multi-staged asynchronous transfer mode (ATM) switching elements to provide fast speed and high bandwidth data transmission capabilities. A challenge in such systems is to assign a virtual circuit path or a virtual circuit identification (VCI) mapping to each switching element to maximize the utilization and throughput of the interconnection network and to satisfy any specific traffic pattern requirements for the network overall. For example, a path conflict may occur within an interconnection network. Such conflicts can occur when input traffic from two different input source ports uses the same physical path on one data path controller (DPC) to two different output destination ports. A conflict means that these two traffic paths cannot be utilized simultaneously to provide full bandwidth.
In one known router configuration, the router has 128 input ports that act as points of “ingress” and 128 destination ports or ports on the “egress” of the router. From the ingress side to the egress side of the router, distribution of the data is often allocated such that the data is transmitted arbitrarily and so that the data traffic is heavier on certain paths. This often results in a bottleneck of the data within the router. Compounding this problem is the inclusion of switching elements with varying data transmission speeds. These switching elements may require that data be split into various multiple paths for proper operation.
For example, with many modern-day router system architectures, data is routed using an allocation scheme that supports single-port high speed switching elements from multiple ports off a multi-port board. Thus, data traffic from all the ports of a low speed board has to be aggregated to a single high speed board by multiple paths in parallel without conflicts. Similarly, traffic from a high speed switching element may be deaggregated into multiple ports for a given low speed board. To support communications between two high speed switching elements, the traffic has to be split evenly into smaller multiple paths or “stripes” and sent to multiple ports in a first stage. Through multiple non-conflict paths, which are preallocated in the interconnection network, traffic must then be aggregated in a last stage to a desired output port. Dividing and reassembling the data into the required multiple paths for the various boards can lead to conflicts in the routing of the data which can result in severe congestion.
Therefore, what is needed are a method and system in which traffic between a source and a destination is evenly transmitted between stages in the interconnection network so that no conflict arises from the transmission of data.